1. Field of the Invention
The present invention relates to an output circuit for use in the output section of a semiconductor integrated circuit, designed to output signals to a device provided outside the semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 shows conventional output circuit which is designed for use in a semiconductor integrated circuit and which is driven by two respective power supplies. A first output circuit 51 generates a signal from an input signal IN. A second output circuit 52 generates a signal OUT from the output signal of the first output circuit 51. To be more specific, the output signal of the circuit 51 is supplied through a signal line 53 to the input terminal of the circuit 52. Both output circuits 51 and 52 have their signal-outputting states determined by the signals input to them. For example, the state of the signal line 53 is determined by the signal IN input to the output circuit 51. The signal line 53 is terminated at a resistor 54 to prevent the output signal of the circuit 51 from undergoing propagation reflection.
Power-supply potential Vcc is applied to the second output circuit 52, whereas the power-supply terminal of the first output circuit 51 is connected to either the Vcc power supply or the ground, by operating a switch SW. In the instance of FIG. 1, the power-supply terminal of the circuit 51 is connected to the ground. In the first output circuit 51, a diode 55 is connected between the power-supply terminals and the output terminal.
Both output circuits 51 and 52 may be of CMOS structure. In this case, the first output circuit 51 has the specific structure of FIG. 2. As shown in FIG. 2, the circuit 51 comprises a P-channel MOS transistor 61, an N-channel MOS transistor 62 and a pn-junction diode 63--all provided in the output section. The P-type drain diffusion layer of the P-channel MOS transistor 61 and the N-type drain diffusion layer of the N-type MOS transistor 62 are connected to the signal line 53. The pn-junction diode 63 is a parasitic one connected between the drain of the P-channel MOS transistor 61 and the back gate (i.e., substrate) of the output circuit. The pn-junction diode 63 is identical to the diode 55 shown in FIG. 1.
Assume that the switch SW connects the power-supply terminal of the first output circuit 51 to the ground as shown in FIG. 1. Then, the built-in potential Vf of the diode 55 is lower than the power-supply potential Vcc applied to one end of the resistor 54. Namely, Vf&lt;Vcc. The diode 55 is forwardly biased, whereby a current I flows from the Vcc power supply to the ground through the diode 55 and the switch SW.
To prevent the current I from flowing this way, the output section of the first output circuit 51 may comprise N-channel MOS transistors only, as illustrated in FIG. 3. The output section of the circuit shown in FIG. 3 comprises two N-channel MOS transistors 62 and 64. The gate of the N-channel MOS transistor 64 receives a control signal, which an inverter 65 has generated by inverting an input signal. The input signal is supplied as a control signal to the gate of the second N-channel MOS transistor 62.
Comprising N-channel MOS transistors only, the output section of the circuit (FIG. 3) can output the ground potential to the signal line 53. The power-supply potential Vcc the circuit outputs, however, decreases by the threshold voltage of the N-channel transistor 64.
In the conventional output circuit 51, as mentioned above, a current flows from the power supply (i.e., Vcc) to the ground via the diode 55 connected at one end to the signal line 53 and at the other end to the power supply, when a power-supply potential (i.e., the ground potential) is applied to the circuit 51, which is different from the potential applied to the other end of the resistor. If measures are taken to prevent such a current flow, the output circuit 51 may fail to generate a sufficiently high output potential.
A conventional tristate output circuit and its problems will be described. In an electronic apparatus such as a computer, signals are transferred through a common bus line. FIG. 4 shows a typical example of bus-line application. To the bus line 71 there are supplied signals from two tristate buffer circuits 72 and 73 which are output circuits. Both tristate buffers 72 and 73 are of CMOS structure. The first tristate buffer 72 generates a signal from an input signal IN1 and supplies the signal to the bus line 71 when the enable signal EN1 supplied to it is active. Similarly, the second tristate buffer 73 generates a signal from an input signal IN2 and supplies the signal to the bus line 71 when the enable signal EN2 supplied to it is active. The outputs of both buffers 72 and 73 remain in high-impedance state when the enable signals EN1 and EN2 are inactive.
A power-supply potential Vcc is applied to the second tristate buffer 73. Either the power-supply potential Vcc or the ground potential is applied to the first tristate buffer 72 through a switch SW. In the instance of FIG. 4, the switch SW connects the buffer 72 to the ground. The buffer 72 comprises a diode 74, which is connected between the input terminal and the power-supply terminal.
Either tristate buffer has the MOS structure shown in FIG. 5. As seen from FIG. 5, the output section of the buffer comprises a P-channel MOS transistor 81 and an N-channel MOS transistor 82. Supplied to the gate of the P-channel MOS transistor 81 is a control signal generated by a NAND circuit 84. The NAND circuit 84 receives the input signal IN and the output signal of an inverter 83. The inverter 83 inverts the enable signal EN. Supplied to the gate of the N-channel MOS transistor 82 is a control signal generated by a NOR circuit 85 which receives the enable signal EN and the input signal IN. The P-type drain diffusion layer of the P-channel MOS transistor 81 and the N-type drain diffusion layer of the N-channel MOS transistor 82 are connected to the output node 86. A parasitic pn-junction diode 87 is therefore formed between the output node 86 and the back gate of the P-channel MOS transistor 81. The pn-junction diode 87 is identical to the diode 74 shown in FIG. 4.
Assume that the switch SW connects the power-supply terminal of the first tristate buffer 72 to the ground as illustrated in FIG. 4, and that the second tristate buffer 73 outputs a Vcc-level signal. Then, the built-in potential Vf of the diode 74 is lower than the power-supply potential Vcc. Namely, Vf&lt;Vcc. The diode 74 is forwardly biased, whereby a current I flows from the Vcc power supply to the ground through the diode 74 and the switch SW.
To prevent the current I from flowing this way, the output section of the tristate buffer may comprise N-channel MOS transistors only, as illustrated in FIG. 6. The output section of the tristate buffer shown in FIG. 6 comprises two N-channel MOS transistors 82 and 88. The gate of the N-channel MOS transistor 88 receives a control signal which a NOR circuit 89 has generated. The NOR circuit 89 receives an enable signal EN and an output signal of an inverter 83. The inverter 83 inverts an input signal IN. The gate of the N-channel MOS transistor 82 receives a control signal generated by a NOR circuit 85 which receives the enable signal EN and the input signal IN, as in the tristate buffer illustrated in FIG. 5.
Comprising N-channel MOS transistors only, the output section of the buffer (FIG. 6) can output the ground potential from the output node 86. The power-supply potential Vcc it outputs, however, decreases by the threshold voltage of the N-channel transistor 88.
In the conventional tristate buffer (i.e., an output circuit) connected to another tristate buffer by a bus line, as described above, a current flows from the other buffer to the ground via the parasitic diode 87, when the power-supply potential is the ground potential while the buffer remains off. If measures are taken to prevent such a current flow, the tristate buffer may fail to generate a sufficiently high output potential.